Phase locked loops provide a very precise reference frequency. Furthermore PLLs can be used to multiply or divide clock signals. For example an input clock of 10 Mhz can be multiplied by the PLL to produce a 1000 Mhz output signal. Phase locked loops are often used to control the frequency of radio receivers or transmitters.
In many devices that include radio receivers and/or transmitters, power conservation is of great concern. For example, in battery powered devices, low power consumption is desired in order to extend the operating time of the battery.
In some devices that include radio receivers or transmitters, the radio is only operative periodically for short intervals. In such devices the PLL that controls the frequency of the radio is operative for the entire time that the radio is operative.
The method and system described herein is directed to decreasing the amount of power consumed by a PLL that is only periodically operative for short intervals.